Description
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Bachelors(Masters) in EE/EC/CS with 5 or Master+4 years digital design verification
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Extensive experience in ASIC/FPGA design and verification flows.
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Familiarity with modern verification practices including System Verilog, UVM and assertion based test
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Experience and knowledge of Processor verification, AXI protocol
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Expertise in Scripting languages like Perl/Python, etc.
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Excellent written and verbal
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communication skills.
Education Requirements
Bachelors or Masters in EE/EC/CS
Years of Experience
Bachelors with 5+ or Masters with 4+years digital design verification